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32 BIT PROCESSOR DATA FLOW SCHEME
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| 32 BIT PROCESSOR DATA FLOW SCHEME |
Prоѕеѕоr :
Cache (retentiveness) inward a processor is rattling pocket-size, while the processor takes more time to access retention (RAM) because it has to transcend through the due north span motorbus. Processors alongside 32 bits have got L1 cache retentivity of 64 Kb as well as for L2 cache retentivity of 512 Kb.
Mеmоrі :
Data is transferred through the north bridge to the processor therefore that it blocks as well as slows downward the fourth dimension it takes.
Nоrth brіdgе :
Regulate the menses of information from as well as to the processor, retention, as well as complimentary bill of fare (AGP Card), every bit good every bit forrad the menstruation of information to and from the S span thence that the data period in the 32 bit method cannot piece of work optimally in supporting processor speed functioning.
64 BIT PROCESSOR DATA FLOW SCHEME
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| 64 BIT PROCESSOR DATA FLOW SCHEME |
Mеmоrі :
The memory is connected straight to the processor via the information line (motorbus) to go rid of the total of time wasted when delivering data. In the previous type (32 scrap processor), information is transferred through the north span to the processor thus that it slows downward the required fourth dimension.
Nоrth brіdgе:
Is a chip that is on the mainboard PC. Functions to regulate data period betwixt the processor together with the graphics card AGP port (accelerated graphics port) as well as too for CSA-type networks (CSA-Network). In addition, this chip is ordinarily located more or less the processor so it is called the N span.
Grаhісѕ аrd:
Graphics cards (costless cards) can telephone exchange information with faster processors, depending on the north span chip and must likewise be supported by newer AGP graphics drives (such every bit ATI or Nvidia products).
CSA-Nеtwоrk:
With 64-bit processors, motherboards are at present equipped with gigabit-controllers, much similar GSA-Network article of furniture. Network functioning is expected to live optimal because the network controller depends on the northward bridge chip. When compared alongside the criteria PCI procedure, the PCI network controller does the slowest chore because it passes through the due south span chip information path.
Sоuth brіdgе:
This chip functions to support processor performance together with is responsible for controlling information catamenia to diverse drives, menu equipment, too other I / O such every bit USB, PS / 2, sound, in addition to parallel or serial ports. All processor commands will live shared here on need. The southward bridge chip is located at the bottom of the mainboard.
Drіvе tоgеthеr wіth аrd:
Communication of data lines from the difficult disk, sound, in addition to other hardware, volition be controlled by the south bridge chip that wants to call the processor via the N span chip.
Dаtа mеnѕеѕ:
Thе іnfоrmаtіоn fаtwа раth, іѕ саllеd thе bu раrtісulаr. ѕеrvеѕ tо реrіоd dаtа tо dіvеrѕе tуреѕ оf соmmроnеn. In thе 64 сhір rоѕеѕоr ѕуѕtеm, thе раth ѕіzе vаrіеѕ. Thіѕ роwеr tо bасk uр grе hаrdwаrе іnwаrd реrfоrmіng орtіmаl реrfоrmаnсе. If уоu lоt uѕаgе оnе-tіmе hаrdwаrе ѕо іt vоlіtіоn nоt lіvе аblе tо bасk uр 64 flесk rоѕеѕоr рrоblеmѕ.